1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device and, in particular, to a semiconductor device including a field effect transistor and a method of manufacturing the semiconductor device.
2. Description of Related Art
A FinFET (Fin Field Effect Transistor) has been known as one of field effect transistors. The FinFET has a device structure considered to be promising in a device using the technology of the 22 nm-node and thereafter. The FinFET has the following merits that the FinFET has higher resistance to short channel effect and can reduce random variations in impurities as compared with a Planar FET (Planar Field Effect Transistor). In this manner, the FinFET has an advantage in constructing a transistor having a very small gate length and hence has been developed with the progress of fine miniaturization of LSI (Large Scale Integration) circuit.
As one example of the Fin FET, a semiconductor device and a method of manufacturing the same are disclosed in Japanese Patent Publication No. JP2005-86024A (patent literature 1 corresponding to U.S. Pat. No. 7,129,550 (B2)). This semiconductor device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate and shaped like a fin that is long in a first direction and that is short in a second direction intersecting the first direction; a gate insulating layer formed on a side surface of the second direction of the semiconductor layer; a gate electrode arranged next to the gate insulating layer; a channel region formed at a position adjacent to the gate insulating layer in the semiconductor layer; source/drain extension regions formed at positions adjacent in the first direction to the channel region in the semiconductor layer; and source/drain regions formed at positions adjacent in the first direction to the source/drain extension regions in the semiconductor layer. The semiconductor device is characterized in that the width in the second direction of the semiconductor layer in the channel region is narrower than the width in the second direction of the semiconductor layer in the source/drain regions.
Further, as a relating technology, a technology of a FinFET is disclosed in “FinFET Performance Advantage at 22 nm: An AC perspective” by M. Guillorn, et al., 2008 Symposium on VLSI Technology Digest of Technical Papers, pp. 12-13 (2008) (non-patent literature 1). This literature discloses a fact that one disadvantage of the FinFET is large parasitic resistance. The literature also discloses a technology for epitaxially growing silicon in the source/drain regions (SD regions) to reduce the parasitic resistance as a method of solving the disadvantage.
Still further, as another relating technology, a hybrid planar and FinFETCMOS device is disclosed in Japanese Patent Publication JP2005-19996A (patent literature 2 corresponding to U.S. Pat. No. 6,911,383 (B2)). A method for forming this integrated semiconductor circuit includes: a step of providing a silicon-on-insulator structure including at least one top semiconductor layer arranged on an embedded insulating layer, the top semiconductor layer including at least one patterned hard mask arranged in a FinFET region of the structure and at least one patterned hard mask arranged in a FET region of the structure; a step of protecting the FET region and trimming the at least one patterned hard mask in the FinFET region; a step of etching such an exposed portion of the top semiconductor layer that is not protected by the hard mask stopping over the embedded insulating layer to thereby form a FinFET activating device region and a FET activating device region, the FinFET activating device region being vertical to the FET activating device region; a step of protecting the FinFET activating device region and of thinning the FET activating device region to thereby make the FET activating device region smaller in height than the FinFET activating device region; a step of forming a gate dielectric on respective exposed vertical surfaces of the FinFET activating device region and of forming a gate dielectric on an exposed horizontal surface of the FET activating device region; and a step of forming a patterned gate electrode on the respective exposed surfaces of the gate dielectric body.
Still further, an integrated circuit chip and a method for manufacturing the same are disclosed in Japanese Patent Publication No. JP2004-88101A (patent literature 3 corresponding to U.S. Pat. No. 7,163,851(B2)). This integrated circuit chip includes at least one fin-type field effect transistor and at least one thick body device. In this integrated circuit chip, the at least one fin-type field effect transistor and the at least one thick body device are formed at the same time.
Still further, a semiconductor device and a method of manufacturing the same are disclosed in International Publication No. WO2005/020325 (patent literature 4). This semiconductor device has a MIS-type field effect transistor including: a semiconductor projecting portion projecting from a plane of a substrate; a gate electrode extending on both opposite side surfaces from a top surface of the semiconductor projecting portion so as to straddle the semiconductor projecting portion; an insulating film formed between the gate electrode and the semiconductor projecting portion; and source/drain regions. This semiconductor device has a plurality of kinds of transistors formed as MIS-type field effect transistors in one chip, the transistors being different from each other in width W in a direction that is parallel to the plane of the substrate in the semiconductor projecting portion below the gate electrode and that is vertical to a channel longitudinal direction.
We have now discovered the following facts.
A semiconductor device is composed of a core transistor that primarily performs a logical operation and a high withstand voltage I/O transistor that performs data input from and data output to the outside. A case where these transistors are manufactured by using a FinFET will be studied.
In a process of forming an impurity layer, extension implant and halo implant need to be performed not only to the top portion of a fin but also to the side plane thereof so as to make a channel plane. However, in the case where a plurality of fins are formed, the spacing between the fins is narrow and hence when a typical ion implantation apparatus is used, a shadowing effect is caused to thereby make it difficult to implant ions. Thus, it has been studied that plasma doping is used for forming the FinFET in place of ion implantation. When the plasma doping is used for a process of forming the impurity layer of the FinFET, even if the spacing between the fins is narrow, impurities can be implanted into the channel plane by dispersion and diffusion of the impurities. However, in the case where the plasma doping is used, since the plasma doping is based on the principle of dispersion and diffusion of the impurities, the impurities cannot be deeply implanted as compared with the case where ion implantation is used. Thus, a mask oxide film used for the plasma doping needs to be made as thin as possible.
Here, the high withstand voltage I/O transistor needs to have a gate insulating film made thicker than the core transistor. In this case, there is brought about the following state: after a fin gate is formed, the core transistor has an oxide film having a thickness of, for example, 2 nm or less formed in the source/drain regions (SD regions) thereof but the high withstand voltage I/O transistor has an oxide film, which is thicker than that of core transistor, formed in the SD regions thereof. In this state, the implanting of impurities into the extension regions by the plasma doping is thought to be difficult. Therefore, in the FinFET, it is difficult to increase the thickness of the gate insulating film to increase the withstand voltage.
In this manner, in a semiconductor device using the technology of the 22 nm-node and thereafter, the manufacturing of the core transistor and the I/O transistor by using the FinFETs is thought to be extremely difficult.